Rethinking Semiconductor Device Design, From the Atoms Up
Speaker
Manasa Kaniselvan
PhD candidate, Computational Nanoelectronics Group, ETH Zurich
About This Talk
Semiconductor devices, such as transistors or memory cells, are changing rapidly to meet the demands of energy-efficient computing. Today’s devices are already miniaturized to atomic levels, while those being designed for the future involve new operating mechanisms, such as phase change or ionic diffusion. In all cases, we see effects which can no longer be captured by the Technology Computer Aided Design (TCAD) tools which sustained decades of Moore’s scaling.
In this seminar, Kaniselvan will motivate a new paradigm in computational device design which starts ’from the atoms up’. Taking resistive memory as an example, she will first introduce how specialized atomistic modelling approaches can help us (1) answer questions about their operating mechanisms and limitations, and (2) uncover methods to boost their performance. She will then introduce a more general framework to simulate current flow through complex materials in the presence of structural changes. Building such a framework requires rapid electronic structure computations during atomic structural evolutions; Kaniselvan will present developments in Machine Learned (ML) property models that enable us to compute these properties at the device-scale. Finally, she will outline how property models for the electronic and vibrational structure of materials can be combined with advanced non-equilibrium transport solvers to model the flow of electrical current across complex interfaces, through statistical distributions of disordered materials, and in the presence of thermal stresses. Together, these tools will enable computational co-design of materials and device geometry for the next generations of semiconductor technology.
About the Speaker
Manasa Kaniselvan is a PhD candidate in the Computational Nanoelectronics Group at ETH Zurich, working with Dr. Mathieu Luisier. Her research aims to design and understand semiconductor devices at atomic resolution, by bridging computational materials science with electronic device modelling. She previously worked with teams at Samsung Semiconductor and Meta FAIR (Fundamental AI Research) Chemistry, where she contributed to semiconductor device/process simulations and built scalable electronic property models. Her work has been recognized with the National Science and Engineering Research Council of Canada (NSERC) PGSD-3 award, highlighted at the Device Research Conference in 2025, and featured on the cover of ACS Nano in 2023 and 2025.