Capability-to-Latency-Energy-Amount-Resistance (CLEAR) metric

Abstract:

Continuing demands for increased computing efficiency and communication bandwidth have pushed the current semiconductor technology to its limit. This led to novel technologies with the potential to outperform conventional electronic solutions such as photonic pre-processors or accelerators, electronic-photonic hybrid circuits, and neural networks. However, the efforts made to describe and predict the performance evolution of compute-performance fall short to accurately predict and thereby explain the actually observed development pace with time; that is all proposed metrics eventually deviate from their development trajectory after several years from when they were originally proposed. This discrepancy demands a figure-of-merit that includes a holistic set of driving forces of the compute-system evolution. Here we introduce the Capability-to-Latency-Energy-Amount-Resistance (CLEAR) metric encompassing synchronizing speed, energy efficiency, physical machine size scaling, and economic cost. We show that CLEAR is the only metric to accurately describe the historical compute-system development. We find that even across different technology options CLEAR matches the observed (post-diction) constant rate-of-growth, and also fits proposed future compute-system (prediction). Therefore, we propose CLEAR to serve as a guide to quantitatively predict required compute-system demands at a given time in the future.

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